Arthur Besse@lemmy.ml to

RISC-V@lemmy.ml · 20 days ago

China's SpacemiT develops "VitalStone V100" 64-core RISC-V datacenter CPU on 12nm

www.tomshardware.com

1

cross-posted to:
hardware@lemmy.world

14

China's SpacemiT develops "VitalStone V100" 64-core RISC-V datacenter CPU on 12nm

www.tomshardware.com

Arthur Besse@lemmy.ml to

RISC-V@lemmy.ml · 20 days ago

1

cross-posted to:
hardware@lemmy.world

China's SpacemiT develops 64-core RISC-V datacenter CPU on 12nm

www.tomshardware.com

Another datacenter-oriented processor from China.

You must log in or register to comment.

Chat

merthyr1831@lemmy.ml
link
fedilink
English
arrow-up
4·
20 days ago
Do we have cores beyond the performance of the c910 yet? Im hoping to see RISCV get to ARM A72+ this year

RISC-V@lemmy.ml

You are not logged in. However you can subscribe from another Fediverse account, for example Lemmy or Mastodon. To do this, paste the following into the search field of your instance: !riscv@lemmy.ml

RISC-V (pronounced “risk-five”) is a license-free, modular, extensible instruction set architecture (ISA).

Youtube | Twitter

Other RISC-V communities on Lemmy

Visibility: Public

This community can be federated to other instances and be posted/commented in by their users.

1 user / day
54 users / week
88 users / month
88 users / 6 months
1 local subscriber
943 subscribers
54 Posts
4 Comments
Modlog

mods:
testman@lemmy.ml